1. Field of the Invention
The present invention generally relates to dual-recessed gate field-effect transistors (FETs), especially monolithic-microwave-integrated-circuit (MMIC) metal-semiconductor field-effect transistors (MESFETs) fabricated on semi-insulating gallium arsenide (GaAs) substrates, with high breakdown voltages provided by offsetting the channel recesses toward the drains of the transistors.
2. Description of the Related Art
A MESFET includes a source and drain formed in a semiconductor substrate, and an active channel region formed in the substrate between the source and drain. A metal gate is formed over the channel region for controlling current flow therethrough in accordance with a voltage applied to the gate.
In order to reduce the source and drain parasitic resistances, a recess is commonly formed in the channel region, and the gate is formed in the recess. The performance of the MESFET can be further enhanced by providing a dual-recessed gate configuration, including a gate recess formed in the channel recess, to enhance the ability of the depletion region under the gate to modulate the channel current under negative gate bias.
A conventional dual-recessed gate MMIC MESFET 10 is illustrated in FIG. 1. The basic design of the MESFET 10 is described in a textbook entitled "GALLIUM ARSENIDE PROCESSING TECHNIQUES", by R. Williams, Artech House, 1984, pp. 61-71. The MESFET 10 is a unit cell which can be fabricated in parallel with a plurality of similar MESFETs in a MMIC circuit configuration to provide a high power MMIC amplifier. Such an arrangement is disclosed in an article entitled "A 2.5 WATT X-BAND HIGH EFFICIENCY MMIC AMPLIFIER", by V Hwang et al, IEEE 1990 Microwave and Millimeter-Wave Monolithic Circuits Symposium, pp. 39-41.
The MESFET 10 includes a semi-insulating semiconductor substrate 12, typically in the form of a GaAs wafer. A heavily doped N-type source 14 and drain 16 are formed in the substrate 12. A lightly doped N-type active channel region 18 is formed in the substrate 12 between the source 14 and drain 16.
A channel recess 20 is formed in the surface of the channel region 18, and a gate recess 20 is formed in the surface of the channel recess 20 to provide a dual-recess configuration. A metal gate 24 is formed in the gate recess 22 to form a Schottky barrier with the underlying portion of the channel region 18. An ohmic source pad 26 is formed on the source 14, and a similar pad 28 is formed on the drain 16.
In the conventional MESFET 10, the channel recess 20 is centered between the source 14 and drain 16, the gate recess 22 is centered in the channel recess 20 and the gate 24 is centered in the gate recess 22. The length and depth of the channel recess 20 and gate recess 22 involve design tradeoffs between parasitic resistance, feedback capacitance, breakdown voltage and other parameters, and are determined empirically for a particular design.
Breakdown voltage is one of the most important parameters in the design of FETs for MMiC power amplifiers. The configuration of FIG. 1 has a breakdown voltage of approximately 12 to 15 volts. The recessed gate configuration increases the breakdown voltage as discussed in an article entitled "Surface Potential Effect on Gate-Drain Avalanche Breakdown in GaAs MESFET's", by H Mizuta, in IEEE Transactions on Electron Devices, Vol. ED-34, No. 10, Oct. 1987, pp. 2027-2033.
Operation at higher voltages enables the power handling capability and efficiency of an FET to be increased. However, higher voltage operation has been limited by the relatively low breakdown voltage of the conventional MESFET design.